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CHIP DESIGN FOR SUBMICRON VLSI : CMOS LAYOUT AND SIMULATION.

By:

UYEMURA, JOHN P

Material type:

TextLanguage: Â Â ENGLISH Publication details: NEW DELHI; CENGAGE LEARNING PVT. LTD.Edition: 2010Description: 411Subject(s):

Â Â VLSI DESIGN

DDC classification:

621.395.395
UYE

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Holdings
Item type	Current library	Home library	Call number	Status	Notes	Barcode
Text Books	PCCOE	PCCOE	621.395.395 (Browse shelf(Opens below))	Available	E AND TC	PCCOEEC17365

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Previous	621.395.395 FUNDAMENTALS OF DIGITAL LOGIC DESIGN WITH VHDL.	621.395.395 CHIP DESIGN FOR SUBMICRON VLSI : CMOS LAYOUT AND SIMULATION.	621.395.395 CHIP DESIGN FOR SUBMICRON VLSI : CMOS LAYOUT AND SIMULATION.	621.395.395 CHIP DESIGN FOR SUBMICRON VLSI : CMOS LAYOUT AND SIMULATION.	621.395.395 CHIP DESIGN FOR SUBMICRON VLSI : CMOS LAYOUT AND SIMULATION.	621.395.395 DESIGN WITH OPERATIONAL AMPLIFIRES AND ANALOG INTEGRATED CIRCUITS.	621.395.395 DESIGN WITH OPERATIONAL AMPLIFIRES AND ANALOG INTEGRATED CIRCUITS.	Next

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