DIGITAL SYSTEMS DESIGN WITH FPGA IMPLEMENTATION USING VERILOG AND VHDL. (Record no. 138535)

MARC details
000 -LEADER
fixed length control field 00522nam a2200205Ia 4500
041 ## - LANGUAGE CODE
Language code of text/sound track or separate title   ENGLISH
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.392
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Item number UNS
100 ## - MAIN ENTRY--AUTHOR NAME
Personal name UNSALAN, CEM
245 #0 - TITLE STATEMENT
Title DIGITAL SYSTEMS DESIGN WITH FPGA IMPLEMENTATION USING VERILOG AND VHDL.
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication CHENNAI
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Name of publisher MCGRAW HILL EDUCATION
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Year of publication 2018
300 ## - PHYSICAL DESCRIPTION
Number of Pages 384
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term   DIGITAL SYSTEMS DESIGN WITH FPGA
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name TAR, BORA
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Reference
Holdings
Full call number Disc Net Amount Accession Number Cost, replacement price Price effective from Koha item type Department Lost status Damaged status Not for loan Withdrawn status Permanent Location Current Location Date acquired Source of acquisition Cost, normal purchase price Bill No Bill Date Language
621.392 25 487.5 PCCOEEC35005 650.00 02/09/2022 Reference E AND TC         PCCOE PCCOE 15/10/2018 SUYOG ENTERPRISES 650.00 S/SI/18-19/5212 2018-10-15 ENGLISH